Transistors typically include semiconductor regions used to form the source regions and drain regions. The contact resistance between metal conductive vias and the semiconductor regions is high. Accordingly, metal silicides are formed on the surfaces of the semiconductor regions such as silicon regions, germanium regions, silicon germanium regions in order to reduce the contact resistance. The conductive vias are formed to contact the silicide regions, and the contact resistance between the conductive vias and the silicide regions are low.
A typical silicidation process includes forming a metal layer on the surfaces of the semiconductor regions, and then performing an annealing, so that the metal layer reacts with the semiconductor regions to form the silicide regions. After the reaction, the upper portions of the metal layer may be left un-reacted. An etch back operation is then performed to remove the un-reacted portions of the metal layer. However, general etch back operation may induce profile kink of the metal layer, and the profile kink may shrink the contact plug critical dimension window. On the other hand, heavy etch operation may cause bottom silicide layer damage.